This page contains the layouts of the Nangate FreePDK45 Generic Open Cell Library automatically generated by EDA tools for automatic transistor placement and detailed routing.

The layouts are honoring a set of litho-friendly design rules defined on a virtual grid of regular fabrics with two metal layers. All layouts have been checked for DRC and LVS correctness.

Detailed routing has been calculated using a satisfiability-based approach with a post-process for wirelength minimization. The symbolic layout using the underlying virtual grid is also shown for each cell.

The information reported for every cell is the following:

In order to view and interact with the symbolic layout in 3D, you need a recent browser with WebGL support to properly display and interact with this page. Support deppends on your browser, your system and your graphics card. Tested with Chrome under Mac and Chrome under Linux.

Please read the Nangate Open Cell Library License.