Patents
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[CSTL13]
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J. Cortadella, V. Singhal, E. Tuncer, and L. Lavagno.
Variability-aware scheme for high-performance asynchronous circuit
voltage regulation, October 2013.
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[CLT13]
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J. Cortadella, L. Lavagno, and E. Tuncer.
Network of tightly coupled performance monitors for determining the
maximum frequency of operation of a semiconductor IC, May 2013.
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[CLMM13]
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J. Cortadella, L. Lavagno, C. Macián, and F. Martorell.
Asynchronous scheme for clock domain crossing, April 2013.
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[SKCL11]
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C. Sotiriou, A. Kondratyev, J. Cortadella, and L. Lavagno.
Asynchronous, multi-rail, asymmetric-phase, static digital logic
with completion detection and method for designing the same, January 2011.
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[CST10]
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J. Cortadella, V. Singhal, and E. Tuncer.
Variability-aware scheme for asynchronous circuit initialization,
April 2010.
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[KC10]
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M. Kishinevsky and J. Cortadella.
Synchronous elastic designs with early evaluation, February 2010.
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[CKL09]
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J. Cortadella, A. Kondratyev, and L. Lavagno.
Skew insensitive clocking method and apparatus, December 2009.
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