GAVINA: Seagull, in Catalan


Group on
Algorithms for VLSI
Design Automation



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The limitations of the human brain are the main bottleneck for building complex systems. A designer rarely has the intellectual capability for reasoning about the interaction of more than a dozen entities simultaneously. For this reason, paradigms such as hierarchy, abstraction and partitioning are the key-stone to build castles with small bricks.

When the amount of information to handle is unmanageable, we resort to computers, since they have the speed and the storage capability to manipulate large amounts of data in short time. Still, some problems are so complex that computers cannot run fast enough to provide the best solution in a reasonable period of time. It is then when we devise strategies that produce sub-optimal solutions with acceptable quality and in affordable computation times.

Correctness is also one of the main concerns of hardware designers, not only for the impact of design errors in the system functionality, but for the enormous manufacturing costs involved in any re-design procedure. Therefore, design automation must also be solidly grounded on formal models.

This is the context in which we do our research, focusing on algorithms for VLSI design automation. The main areas in which we invest our efforts are the following:


Last modified: 9/11/2004 by Jordi Cortadella