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@patent{Mix_Latch,
author = {F. Minnella and L. Lavagno and M. Casu and J. Cortadella},
title = {{A method for increasing the operating frequency of synchronous digital circuits using a single clock tree
and a mixed distribution of sequential elements}},
type = {patentus},
number = {WO 2024/209409 A1},
url = {https://patentscope.wipo.int/search/en/detail.jsf?docId=WO2024209409},
holder = {{Politecnico di Torino and Universitat Politècnica de Catalunya}},
date = {2024-10-10},
year = 2024,
month = oct,
day = 10,
datefiled = {2024-04-5},
abstract = {A method for increasing the operating frequency of a synchronous digital circuit, starting from a sequential electronic circuit based on Flip-Flops, comprising the steps of: - synthesizing said sequential electronic circuit based on Flip-Flops starting from a register transfer level (RTL) description of said sequential electronic circuit based on Flip-Flops; - providing a Positive Edge Triggered Flop (PETF) layout or netlist of said synthesis, and generating a Positive Transparent Latches (PTL) layout by replacing all sequential elements of said Positive Edge Triggered Flop (PETF) layout or netlist with said Positive Transparent Latches (PTL); - creating a graph representation of the timing and positional information extracted from said Positive Transparent Latches (PTL) layout; - defining circuit locations (layouts) of Negative Transparent Latches (NTL), Positive Edge Triggered Flops (PETFs), and Negative Edge Triggered Flops (NETFs) by using a mathematical formulation taking in input said graph represented timing and positional information; - inserting said Negative Transparent Latches (NTL), Positive Edge Triggered Flops (PETFs), and Negative Edge Triggered Flops (NETFs) of said circuit locations (layouts) in said Positive Transparent Latches (PTL) layout obtaining a modified mixed sequential netlist; - generating a final layout of said synchronous digital circuit based on said modified mixed sequential netlist.}
}
@patent{Skew_insensitive,
author = {J. Cortadella and A. Kondratyev and L. Lavagno},
title = {{Skew insensitive clocking method and apparatus}},
type = {patentus},
number = {7,634,749},
url = {http://www.google.com/patents/US7634749},
uspto = {http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7634749},
holder = {{Cadence Design Systems, Inc.}},
date = {2009-12-15},
year = 2009,
month = dec,
day = 15,
datefiled = {2005-04-1},
abstract = {A method of designing a skew insensitive circuit is performed by designing a synchronous circuit including flip-flops and combinatorial logic and, for each flip-flop, inserting logic gates to receive a skewed clock signal and to locally derive non-overlapping clock phases from the skewed clock signal.}
}
@patent{Early_evaluation,
author = {M. Kishinevsky and J. Cortadella},
title = {{Synchronous elastic designs with early evaluation}},
type = {patentus},
number = {7,657,862},
url = {http://www.google.com/patents/US7657862},
uspto = {http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7657862},
holder = {Intel Corporation},
date = {2010-02-02},
year = 2010,
month = feb,
day = 2,
datefiled = {2006-12-06},
abstract = {Embodiments of early enabling synchronous elastic designs, devices and methods are presented herein.}
}
@patent{Elastix_init,
author = {J. Cortadella and V. Singhal and E. Tuncer},
title = {{Variability-aware scheme for asynchronous circuit initialization}},
type = {patentus},
number = {7,701,255},
url = {http://www.google.com/patents/US7701255},
uspto = {http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7701255},
holder = {Elastix Corporation},
date = {2010-04-20},
year = 2010,
month = apr,
day = 20,
datefiled = {2008-11-05}
}
@patent{Multi-rail,
author = {C. Sotiriou and A. Kondratyev and J. Cortadella and L. Lavagno},
title = {{Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same}},
type = {patentus},
number = {7,870,516},
url = {http://www.google.com/patents/US7870516},
uspto = {http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7870516},
holder = {{Institute of Computer Science, Foundation for Research and Technology - Hellas}},
date = {2011-01-11},
year = 2011,
month = jan,
day = 11,
datefiled = {2007-10-25},
abstract = {A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit is provided. A Boolean logic circuit is converted into a first multi-rail circuit using at least Shannon's expansion. The first multi-rail circuit is technology mapped into a second multi-rail circuit. Completion detection circuitry is added which receives the primary outputs of the second multi-rail circuit.}
}
@patent{Clock_Domain_Crossing,
author = {J. Cortadella and L. Lavagno and C. Maci\'an and F. Martorell},
title = {{Asynchronous scheme for clock domain crossing}},
type = {patentus},
number = {8,433,875},
url = {http://www.google.com/patents/US8433875},
uspto = {http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8433875},
holder = {eSilicon Corporation},
date = {2013-04-30},
year = 2013,
month = apr,
day = 30,
datefiled = {2010-02-24}
}
@patent{Monitors,
author = {J. Cortadella and L. Lavagno and E. Tuncer},
title = {{Network of tightly coupled performance monitors for determining the maximum frequency of operation of a semiconductor IC}},
type = {patentus},
number = {8,446,224},
url = {http://www.google.com/patents/US8446224},
uspto = {http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8446224},
holder = {eSilicon Corporation},
date = {2013-05-21},
year = 2013,
month = may,
day = 21,
datefiled = {2011-07-12}
}
@patent{VoltageRegulation,
author = {J. Cortadella and V. Singhal and E. Tuncer and L. Lavagno},
title = {{Variability-aware scheme for high-performance asynchronous circuit voltage regulation}},
type = {patentus},
number = {8,572,539},
url = {http://www.google.com/patents/US8572539},
uspto = {http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8572539},
holder = {eSilicon Corporation},
date = {2013-10-29},
year = 2013,
month = oct,
day = 29,
datefiled = {2008-11-05}
}
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