Logic synthesis

The main problem we try to solve can be stated as follows: given a behavior that can be specified as a Boolean function, what is the most efficient implementation using logic gates?. We typically aim at optimizing the area or delay of the implementation. Our research is now focused on the logic decomposition and technology mapping of multi-level circuits, devising algorithms to solve Boolean relations, using techniques based on BDDs, finding Boolean divisors for decomposition, etc.

As an example of the research in this area, you can have a look at one of our papers, that deserved the best paper award at DAC 2004:

D. Baeres, J. Cortadella and M.Kishinevsky,
A Recursive paradigm to solve Boolean relations,
Design Automation Conference, San Diego, June 2004.
[PDF] [Powerpoint]

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