Screenshot of fpv, the floorplan viewing tool

HiReg is a floorplanner (or more accurately, a suite of floorplanning tools) that generates regular floorplans by automatically identifying repeating subcircuits in the netlist. Regular floorplans use the same layout for repetitions of the same circuit, thereby reducing design complexity.

HiReg was developed as an extension/companion of CMPexplore, a tool for the architectural exploration of hierarchical chip multiprocessors.

HiReg is implemented in C++ and requires a ILP solver such as GLPK or Gurobi, plus Qt4 for the optional graphical tools. It is distributed under the terms of the GPLv3. METIS (included) is distributed under the terms of the Apache License 2.0.


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