ASIC design estimator
Introduction
Designing Application-Specific Integrated Circuits (ASICs) is a demanding process, comprising the "front end" and "place and route" phases. The front end involves creating the chip's functionality in a hardware description language, a meticulous and iterative task. The subsequent "place and route" phase aims to optimally arrange millions of components while minimizing power consumption, area, and delays, which is computationally intensive. Hours or days of runtime are required due to the design size and the complexity of required algorithms. Incremental changes in RTL design can trigger ripple effects, necessitating a full re-run of the process to ensure overall optimization. These challenges underpin the time-intensive nature of ASIC design.
In a company like Marvell, operating on the cutting edge of technology (5nm and 3nm) with chip design cycles spanning months and production costs running into millions of dollars, the imperative to improve productivity cannot be overstated. Time to market is a pivotal factor, as faster design processes allow the company to seize opportunities and stay ahead of competitors in the rapidly evolving tech landscape. Increased productivity accelerates product development, leading to innovative and reliable solutions that strengthen Marvell's market position in a tech industry driven by innovation.
Project
The proposed challenge is to implement a high-level estimation tool for ASIC design, which aims to quickly assess key metrics like area, power, timing, and congestion without the need for a full place and route (P&R) process. Here's an outline of how such a system might work:
Input RTL and Benchmark Database: The system takes RTL code and EDA tool settings to be used in PnR as its input, along with a database of previously executed benchmarks. These benchmarks include data from similar designs and their corresponding P&R results.
Property Extraction: The system extracts relevant properties from the RTL code, including the logic structure, data path, clock domains, and constraints. These properties can be extracted after a synthesis process. Other algorithms to extract properties can be implemented if their timing complexity is low.
Algorithmic Estimations: The main goal of the system is to use these fast extracted metrics to estimate what would be the final results if the long PnR process is executed. The system accuracy can be evaluated using existing benchmarks.
Comparison with Benchmark Data: system compares the extracted metrics with the benchmark database. This allows it to identify similar designs and assess how well they align with those previous results.
Report and Recommendations: The system generates a report that includes estimated area, power, timing, and congestion metrics. It also provides recommendations and insights, such as potential bottlenecks or areas for optimization.
Iterative Refinement: The user can iteratively refine the design based on the system's estimations and recommendations. This process can help in making informed decisions about design trade-offs and optimizations before committing to a full P&R flow.
By offering fast estimations, this system can significantly reduce the turnaround time in the early stages of ASIC design. However, it's important to note that these estimations will have inherent limitations, and a full P&R flow will still be required for precise and validated results.
Requirements
Students pursuing a Master Thesis or a Final Degree Project, with a strong background in Computer/Data Science and/or Mathematics, are eligible, preferably with skills in:
- Algorithms and data structures
- Graph theory
- C++ and python
- Oral and written English
Application
Students interested in this opportunity should contact Jordi Cortadella, Jonas Casanova (jcasanova at marvell.com), and Marc Galceran (mgalceran at marvell.com).
Support
This project will be supported by Marvell, a leading company in the design and manufacturing of semiconductors for cloud networking and automotive.
