Patents

[CSTL13]

J. Cortadella, V. Singhal, E. Tuncer, and L. Lavagno. Variability-aware scheme for high-performance asynchronous circuit voltage regulation, October 2013. [ bib | USPTO | Google ]

[CLT13]

J. Cortadella, L. Lavagno, and E. Tuncer. Network of tightly coupled performance monitors for determining the maximum frequency of operation of a semiconductor IC, May 2013. [ bib | USPTO | Google ]

[CLMM13]

J. Cortadella, L. Lavagno, C. Macián, and F. Martorell. Asynchronous scheme for clock domain crossing, April 2013. [ bib | USPTO | Google ]

[SKCL11]

C. Sotiriou, A. Kondratyev, J. Cortadella, and L. Lavagno. Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same, January 2011. [ bib | USPTO | Google ]

[CST10]

J. Cortadella, V. Singhal, and E. Tuncer. Variability-aware scheme for asynchronous circuit initialization, April 2010. [ bib | USPTO | Google ]

[KC10]

M. Kishinevsky and J. Cortadella. Synchronous elastic designs with early evaluation, February 2010. [ bib | USPTO | Google ]

[CKL09]

J. Cortadella, A. Kondratyev, and L. Lavagno. Skew insensitive clocking method and apparatus, December 2009. [ bib | USPTO | Google ]

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